Browsing by Author "Kelleci,B."

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Citation Count: 5
Design and Analysis of 240 Watt SEPIC Converter for LED Applications
(Institute of Electrical and Electronics Engineers Inc., 2019) Hayirli,I.H.; Kelleci,B.; Kivanc,O.C.; Ozturk,S.B.; Tuncay,R.N.; Citci,M.O.
A 240 Watt output power SEPIC converter with an output voltage of 24 V is proposed to be used in automotive and railway LED applications. The input voltage of the converter varies between 16 V and 36 V. The stability of the converter is guaranteed by moving one of the dominant pole to lower frequency and canceling the other pole with a zero. The phase margin is higher than 56° across all input voltage values. The transients of the switch is damped using a passive snubber circuit. Electromagnetic analyses are performed using Ansys SiWave™ to determine voltage drop, current distribution, near and far field and resonance behavior of SEPIC converter. Measurement results indicate that the SEPIC converter is stable under various operating conditions. © 2019 IEEE.
Citation Count: 1
Recursive odd-even sorter for vector quantizer
(Institute of Electrical and Electronics Engineers Inc., 2017) Atila,B.; Kelleci,B.
A recursive, odd-even transposition sorter based vector quantizer which is used in mismatch shaping algorithms is presented. Although recursive parallel sorting algorithms require less area than fully parallel sorting algorithms, they are slower than fully parallel algorithms. A widely used recursive parallel sorting algorithm is the perfect shuffle which requires multiple clock cycles to shuffle and sort the data. The proposed recursive algorithm uses fewer clock cycles than the perfect shuffle to sort less than 80 inputs. An area efficient version is also proposed to sort less than 16 inputs faster than perfect shuffle algorithm. To compare the performance of various sorting algorithms suitable for vector quantizer, they are realized and synthesized in TSMC 40nm low-power technology. Speed and area results indicate that the proposed algorithm sorts 32 inputs at a 42% faster rate by using 14% fewer components than the perfect shuffle sorter and a 80% slower rate by using 27% fewer components than the Bitonic sorter. The area efficient version sorts 32 inputs at a 21% slower rate by using 32% fewer components than the perfect shuffle sorter. © 2017 IEEE.
Citation Count: 0
Replica bias circuit for common-source amplifier
(Turkiye Klinikleri, 2020) Kelleci,B.
A replica bias circuit to set the current of common-source amplifier to reduce the gain variations across process, voltage, and temperature (PVT) changes is proposed. The gain of a common-source amplifier is set by the load resistor and transistor transconductance which is set proportional to a resistor using a constant-gm bias circuit. The success of constant-gm biasing depends on the accuracy of copying of generated current to the transistor. The leakage current at the transistor gate due to the electrostatic discharge protection diodes prevents the matching of the common source transistor current to the constant-gm circuit current. A low-power replica of the common-source amplifier is used to determine the current error which is minimized using a feedback circuit. Corner simulations indicate that gain variation across PVT reduced to ±1.9 dB using the proposed biasing method as opposed to ±9.9 dB for traditional biasing method for 1 μA leakage current. Monte Carlo simulations with process and mismatch indicate that the standard deviation of the gain is reduced to 0.34 dB from 3.57 dB. © 2020 Turkiye Klinikleri. All rights reserved.