Towards improved parallelism through order reduction of accessing data in nD matrices

dc.authorscopusid16242405400
dc.authorwosidRahnama, Behnam/D-8295-2012
dc.contributor.authorRahnama, Behnam
dc.date.accessioned2024-05-25T11:23:43Z
dc.date.available2024-05-25T11:23:43Z
dc.date.issued2014
dc.departmentOkan Universityen_US
dc.department-tempOkan Univ, Dept Comp Engn, Istanbul, Turkeyen_US
dc.description.abstractThis paper encompasses the presentation of an enhanced approach with the capacity to reduce the time complexity of accessing nodes in m-dimensional matrices from to . The accomplishment of this process is attained by the serialization of nD (nD) matrices to single-dimensional arrays followed by the access of nodes accordingly. Linear representation of nD matrix data structure induces a superior parallelism of matrix calculations over dense, parallel core micro-architecture computers, including NVIDIA GPGPU Supercomputing and Intel Xeon Phi processing boards. This approach is feasibly implemented as the core of matrix data representation in Math software such as Matlab, Mathematica and Maple, in IDEs for more optimized code generation and in Parallel Computing Libraries such as CUBLAS and Magma.en_US
dc.identifier.citation0
dc.identifier.doi10.1007/s11227-014-1271-1
dc.identifier.endpage986en_US
dc.identifier.issn0920-8542
dc.identifier.issn1573-0484
dc.identifier.issue2en_US
dc.identifier.scopus2-s2.0-84919794322
dc.identifier.scopusqualityQ2
dc.identifier.startpage977en_US
dc.identifier.urihttps://doi.org/10.1007/s11227-014-1271-1
dc.identifier.urihttps://hdl.handle.net/20.500.14517/752
dc.identifier.volume70en_US
dc.identifier.wosWOS:000344552400033
dc.identifier.wosqualityQ2
dc.language.isoenen_US
dc.publisherSpringeren_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectMatrix serialization / Deserializationen_US
dc.subjectOrder reductionen_US
dc.subjectMulti-dimensional matricesen_US
dc.titleTowards improved parallelism through order reduction of accessing data in nD matricesen_US
dc.typeArticleen_US
dspace.entity.typePublication

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