Pulse Suppression Technique for Mitigating Digital Clock Noise

dc.authorid KELLECI, BURAK/0000-0002-0961-1153
dc.authorscopusid 16052490500
dc.authorwosid KELLECI, BURAK/X-2533-2018
dc.contributor.author Kelleci, Burak
dc.date.accessioned 2024-05-25T11:24:09Z
dc.date.available 2024-05-25T11:24:09Z
dc.date.issued 2014
dc.department Okan University en_US
dc.department-temp Okan Univ, Coll Engn & Architecture, TR-34959 Istanbul, Turkey en_US
dc.description KELLECI, BURAK/0000-0002-0961-1153 en_US
dc.description.abstract A practical digital clock noise mitigation technique based on pulse removal is presented. Clock frequency is increased to generate an excess pulse, which is removed in order to match the number of pulses in an average time frame. The location of the excess pulse is selected as the same time point or randomly selected in every time frame. Mathematical analyses are presented for both methods. The circuit is implemented using a state machine on a FPGA. Measurement results indicate more than 40 dB improvement on the digital noise level within a band of interest. en_US
dc.identifier.citationcount 0
dc.identifier.doi 10.1007/s00034-013-9697-x
dc.identifier.endpage 1336 en_US
dc.identifier.issn 0278-081X
dc.identifier.issn 1531-5878
dc.identifier.issue 5 en_US
dc.identifier.scopus 2-s2.0-84900550025
dc.identifier.scopusquality Q2
dc.identifier.startpage 1325 en_US
dc.identifier.uri https://doi.org/10.1007/s00034-013-9697-x
dc.identifier.uri https://hdl.handle.net/20.500.14517/771
dc.identifier.volume 33 en_US
dc.identifier.wos WOS:000335582000001
dc.identifier.wosquality Q3
dc.language.iso en
dc.publisher Springer Birkhauser en_US
dc.relation.publicationcategory Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı en_US
dc.rights info:eu-repo/semantics/closedAccess en_US
dc.scopus.citedbyCount 0
dc.subject Digital clock noise en_US
dc.subject Interferer en_US
dc.subject Aggressor en_US
dc.subject Victim en_US
dc.subject Pulse suppression en_US
dc.subject Clock noise en_US
dc.title Pulse Suppression Technique for Mitigating Digital Clock Noise en_US
dc.type Article en_US
dc.wos.citedbyCount 0

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